Electrical circuit

ABSTRACT

A METHOD AND APPARTUS FOR RESISTANCE WELDING CONTROL FOR SENSING THE CONTACT RESISTANCE AT THE WELDING POSITION, TERMINTING WELD CURRENT WITHIN A PREDETERMINED TIME RANGE AND AT A PREDETERMINED FRACTION OF THE VALUE OF THE CONTACT RESISTANCE IF SUCH IS REACHED WITHIN SAID TIME RANGE AND PROVIDING ALARMS INDICATIVE OF PRESENT WELD CONDITION AND IMPENDING DEGRADATION. THE CONTACT RESISTANCE IS DETERMINED BY DETECTING THE AMPLITUDE PEAK OF THE WELD CURRENT WAVEFORM AND THEREUPON CHARGING A STORAGE DEVICE AT A RATE PROPORTIONAL TO THE INSTANTANEOUS ELECTRODE VOLTAGE FOR A RELATIVELY SHORT INTERVAL INVERSELY PROPORTIONAL TO THE PEAK WELD CURRENT AMPLITUDE TO PRODUCE A PULSE OF HEIGHT PROPORTIONAL TO THE INSTANTANEOUS CONTACT RESISTANCE. WELD TERMINATION MEANS RESPONSIVE TO THE INSTANTANEOUS CONTACT RESISTANCE TERMINATES THE WELD CURRENT WHEN THE CONTACT RESISTANCE REACHES A PREDETERMINED FRACTION OF ITS PEAK VALUE OR AT LEAST WITHIN A SELECTED TIME RANGE. A PLURALITY OF TIMERS CAUSE THE WELD TERMINATION MEANS TO TERMINATE WELD CURRENT AT THE BEGINNING OF SAID RANGE IF THE CONTACT RESISTANCE IS LESS THAN SAID PREDETERMINED FRACTION OR AT THE END OF SAID TIME RANGE IF THE INSTANTANEOUS CONTACT RESISTANCE HAS NOT THEN REACHED SAID FRACTIONAL VALUE. ALARMS ARE ACTUATED TO INDICATE QUESTIONABLE OR DOUBTFUL PRESENT WELDS AND IMPENDING PROCESS DEGRADATION.

United States Patent Peter W. Vanderhelst [72] Inventor PrimaryExaminer-J. V. Truhe Livonia, Mich. Assistant Examiner l. G. Smith [2] 1Appl. No 755,158 Attorney-Woodhams, Blanchard and Flynn [22] Filed Aug.26, I968 M [45] Patented June 28,1971 I [73' Assignee Robmmn CorporafionABSTRACT: A method and apparatus of resistance welding Dem). Michcontrol for sensing the contact resistance at the welding position,terminating weld current within a predetermined time range and at apredetermined fraction of the value of the contact resistance if such isreached within said time range and providing alarms indicative ofpresent weld condition and impending degradation. The contact resistanceis determined by detecting the amplitude peak of the weld currentwaveform and thereupon charging a storage device at a rate proportional[54] ELECTRICAL CIRCUIT to the instantaneous electrode voltage for arelatively short in- 34 Claims, 26 Drawing Figs. terval inverselyproportional to the peak weld current amplitude to produce a pulse ofheight proportional to the instan- (52) U.S. Cl 219/117, taneous contactresistance. Weld termination means respon- 219/110 sive to theinstantaneous contact resistance terminates the [5 1] Int. Cl 823k 11/24weld current when the contact resistance reaches a predeter- [50] Fieldof Search. 219/ 108- mined fraction of its peak value or at least withina selected 1 i0, 114 time range. A plurality of timers cause the weldtermination means to terminate weld current at the beginning of saidrange [56] Refe nce Cited if the contact resistance is less than saidpredetermined frac- UMTED STATES PATENTS tion or at the end of said timerange if the instantaneous contact resistance has not then reached saidfractional value. 2,508,330 5/1950 Callender et al 2l9/l l0 Alarms areactuated to indicate questionable or doubtful 3,345.493 10/1967 Guettelet al. 21 9/1 H) present welds and impending process degradation.

CLAMP ven) TIME r :IGN"7QE F'L j 81 L WELD H GH {lNlTlAL Low O J J m? Zifii'i uwr imNKsNe LlMlT 86 LIMIT -11 ff gg PbB imp-E2 ozser q TlMEE iTlMEQ lTlMEQ MEMOQY 87 b 1 4 i 5 V l 72 QESET FlmNa END WELD SIGNAL l LIClECUlT L u l 57A g Li 85 END m WELD f PP CLAMP P- a M PEAK i gf: PULSE3 END PATIO PULSE CLAMP 5'] i 3% l 33 ii l H? P J 2E Q J END 47 I TiME4! SYNCH PATlO 35 DETECTOR 9 42 5 i I GEN'PAT E 2b.v t 0 lu BC I 39Payee ALL 5-05. 5 SU LY l m 3 PATENTEDJuuzamn SHEET 7 BF 7 w r T P Q M TK D W. E A N DP m m E mw T WW WS M M I 18 T M LP T WHT MW It I. M mm -ummME /\N. HTE M 8 U8 8 m l D MO [ILHWMF m nwwm WM D .L /*4 \I I,A U -R MTD4 I W M T I. V. rNuU K wM w A U T NS E C N AME PB? D II LM .A L D B P 2E \L .L I'll}. W E mmm W W 1 w 1 M LN W MM M W W [m ir -('MAX|MUM WELDINTEPVAL QUESHONABLY QUESTIONABLY GOOD GOOD GOOD LIKELY BAD WELD QUALITYT\ME ELECTRICAL CIRCUIT BACKGROUND OF THE INVENTION I. Field oftheInvention This invention relates to a method and apparatus forresistance feedback welding control and more particularly relates tosuch a method and apparatus incorporating an improved, simplified meansfor providing a signal proportional to the instantaneous weld contactresistance for normally terminating the weld in response to the contactresistance sensed and for warning of present or impending questionableor bad welds. 2. Description of the Prior Art 4 It is highly unusual fora common industrial welding machine to produce I percent good weldswithout exceptional maintenance and quality control measures beingtaken. No welding control presently known is capable of providingabsolute quality assurance. It is possible, however, to monitor someprocess variable which is related to weld quality, to make in processadjustments to arrive at the desired state of that variable and, byobservation of the adjustments made, to determine whether or not theprocess is a consistent one.

The process parameter here chosen for monitoring is the change in theweld electrical resistance (contact resistance) that occurs during theweld time. It has been found that the resistance of a spot weld variesaccording to a predictable pattern as the weld is being formed. For thefirst few cycles of welding, the resistance may be erratic due to metalfit and surface condition variables but the general trendis for theresistance to increase as the stock is heated by the weld current. Atsome point in the weld interval, the resistance will peak and then beginto decrease. it is theorized that this decrease in weld resistance isdue to metal fusion and the resulting destruction of the interfaceresistance of the parts to be welded. It is possible to relate thepercentage drop in weld resistance (from the peak value) during the weldtime to weld nugget size. For example, in the welding of two pieces ofclean 0.060 inch mild steel, a resistance drop of IS percent in areasonable weld time with reasonable electrode force will be found toproduce a good weld.

An important advantage of the method based on the above considerationsis the fact that the desirable percentage resistance drop for a givenspot welder changes relatively little as weld current, electrode area,stock thickness or number of layers of stock are varied. As a result, itis possible to arrive with a desired resistance percentage drop settingthat will enable welding of, for example, two pieces of 0.035 inch stockor three pieces of 0.060 inch stock reliably without the need forseparate selectors on the control station.

The basic method resulting from the above consideration is themonitoring of the weld contact resistance (disregarding the first fewerratic cycles), remembering electronically the peak (highest) value ofthe resistance reached during the weld interval and allowing the weldtime to continue until the resistance has decreased by a presetpercentage. Means which have been found highly satisfactory for carryingout such a welding method are disclosed in pending applications Ser.Nos. 650,7l4 and 650,789 assigned to the assignee of the presentinvention.

With respect to method and apparatus for sensing the instantaneous weldcontact resistance, the method and apparatus of above-mentionedapplications Ser. No. 650,714 is reliable and highly accurate and maystill be preferred for certain highly critical applications. However, itls relatively compics in comparison to the method and apparatus of thepresent invention.

Further, the apparatus of the above-mentioned application makes noprovision for detecting slow degradation of process variables such as indamaged and gradually deteriorating secondary welding cable. Such adefect could. if undetected, eventually increase the required weldinterval to a point beyond the maximum tolerable to make the requiredproduction rate. At such time, the welds would turn had and nothingshort of maintenance would restore good welds. Such a condition would behighly disadvantageous if occurring during peak production hours on anassembly line. it would be far better if the slowly changing processparameters could be made to give an early warning that the process wasdrifting so that maintenance could be scheduled for a convenient time.

Thus, it is among the objects and purposes of this invention:

I. To provide a simplified method and apparatus for resistance feedbackwelding control. 2. To provide a simplified method and apparatus, asaforesaid, in which the contact resistance at the weld position issensed and weld current is normally terminated when the contactresistance falls to a preselected fraction of its peak value, suchfraction being referred to as the end ratio. 3. To provide a method andapparatus, as aforesaid, including a simplified method and apparatus forsensing the weld contact resistance which is highly reliable andaccurate and at least to a close degree approaches the accuracy of thecorresponding resistance sensing means of the aforementionedapplications and which, at least for many purposes, may be used insteadof the means of the aforementioned applications. 4. To provide a methodand apparatus of weld contact resistance sensing, as aforesaid, in whichparameters of the weld circuit are sensed and used immediately toprovide an output proportional to contact resistance and in whichcontinuous storage of such parameters is unnecessary. 5. To provide amethod and apparatus of weld contact resistance sensing, as aforesaid,which generates weld contact resistance signal from inputs related tothe weld current and electrode voltage in a manner different from andconsiderably simpler than that of the aforementioned applications andwhich eliminates considerable apparatus including a high frequencyoscillator and flip-flop circuit. 7. To provide a method and apparatusof weld contact resistance sensing, as aforesaid, which directlycombines parameters related to the welding current peak amplitude andthe electrode voltage, taken at the weld current peak, to form an outputof amplitude proportional to the instantaneous weld contact resistance.8. To provide a method and apparatus of weld contact resistance sensing,as aforesaid, which periodically produces pulses of amplitudeproportional to the weld contact resistance and which eliminates thenecessity for, but which is readily adaptable to, pulse averaging toproduce a continuous contact resistance signal output. 9. To provide amethod and apparatus of weld contact resistance sensing, as aforesaid,in which the number of iron core transformers required is substantiallyreduced from the apparatus of the aforementioned applications and inwhich substantial quantities of circuitry are omitted. 10. To provide amethod and apparatus of resistance feedback welding control, asaforesaid, which provides an early warning of shifts in processvariables which if unchecked could result in bad welds, so that requiredcorrective maintenance can be performed at convenient times outside ofnormal production periods and which, in addition, indicates the qualityof welds as they are made.

Other objects and purposes of this invention will be apparent to thoseacquainted with methods and apparatus of this general type upon readingthe following specification and inspecting the accompanying drawings.

in the drawings:

FIG. I is a block diagram of the resistance feedback welding controlembodying the invention.

FIG. 2 is a schematic circuit diagram of the integrator-amplifier, peakpulse, R time base, and synch portions of the weld contact resistancesensing unit of the block diagram of FIG. 1.

FIG. 3 is a schematic circuit diagram disclosing the R generator portionof the weld contact resistance sensing unit of FIG. I together with theend ratio detector and end weld portion ofthe weld terminating unit ofFIG. I.

FIG. 4 is a schematic circuit diagram disclosing the high limit timerand initial blanking timers ol' the weld terminating unit of FIG. I,

FIG. 5 is a schematic circuit diagram disclosing the low limit timer andmemory and lockout timer portions of the weld terminating unit of FIG.I. l

FIG. 6 is a schematic circuit diagram of the alarm unit and power supplyof FIG. 1.

FIGS. 7a--p are diagrams disclosing waveforms found in the circuit ofFIGS. 1-5.

FIG. 8 is a plot of contact resistance versus time disclosing aplurality of weld contact resistance drop characteristics.

FIG. 9 is a modified segment of FIG. 3.

FIGS. 10a, b are diagrams disclosing waveforms resulting from themodification of FIG. 9.

SUMMARY OF THE INVENTION The objects and purposes of this invention aremet by providing a resistance feedback welding control comprising a weldcontact resistance sensing unit and weld current terminating unittogether with quality indicating means. The resistance sensing unitcomprises an air core transformer in the secondary of'the weldingcircuit which detects the rate of change at weld current with respect totime (dl/dl) and applies same to an integrating amplifier. Theintegrating amplifier provides a signal proportional to the weld current(I) which is applied to a peak pulse circuit and an R time base circuit.The peak pulse circuit detects the time at which the peak amplitude ofthe weld current occurs and provides an output at such time. The R timebase circuit provides an output, the duration of which is inverselyproportional to the peak amplitude of the weld current. A weld electrodevoltage sensor senses the electrode voltage E and provides a currentoutput proportional thereto. An R generator circuit responsive to thepeak pulse, R time base and electrode voltage sensing circuits includesstorage means chargeable in response to the output of the peak pulsecircuit at rate determined by the output of the electrode voltage sensorand for a time determined by the R time base circuit to produce anoutput R pulse of amplitude proportional to the weld contact resistance.The method of resistance sensing thus involves determining the time atwhich the weld current peaks, generating a time parameter inverselyproportional to the weld current peak amplitude, detecting the electrodevoltage and generating current proportional thereto and, at the time ofthe weld current amplitude peak, charging storage means with saidcurrent for the duration of said time parameter to provide an outputpotential proportional to the instantaneous weld contact resistance. A

.The weld terminating unit comprises an end ratio detecto whichdetermines when the weld contact resistance has reached a preselectedfraction of its peak value (the end ratio) and an end weld circuitresponsive thereto for terminating the weld current when said contactresistance reaches the end ratio..ln addition, a plurality of timingcircuits cause weld current termination to occur within a preselectedtime range. The

I timing circuits provide alarms upon failure of the weld contactresistance to reach the end ratio within said time range and when theend ratio occurs late in said time range indicating a degradation ofprocess parameters which ultimately may result in a bad weld.

DETAILED DESCRIPTION The resistance feedback welding control 10 (FIG. 1)em bodying the invention is intended for use with a conventionalresistance welding machine indicates in part at 11 and including a weldtimer l2 controlling a firing circuit 13 adapted to supply weld currentto weld electrodes 14 through a welding transformer 16. The weld timer12 may include a suitable interfacing adapter of any convenient type toadapt signal voltages flowing either from or to the control 10 to therequirements of the weld timer 12.

The resistance feedback welding control 10 broadly comprises a weldcontact resistance sensing unit 18 and a weld terminating unit generallyindicated at 19.

A DC power supply 21 of any convenient type supplies DC operatingpotential to the hereinafter described portions of the units 18 and 19through a DC positive potential line 22, a reference or zero potentialline 23 and a positive full wave rectified, unfiltered potential line24.

The weld contact resistance sensing unit 18 includes an air core coil 26which is inductively coupled to the secondary circoil 27 of the weldtransformer 16 for sensing the time rate of change of weld current(dI/dl and an integrating amplifier 28 driven by the coil 26 forproducing a continuous signal voltage I proportional to theinstantaneous weld current. It is contemplated that the preferred aireore coil 26 and integrating amplifier 28 may be replaced by an ironcore transformer though at least at the penalty of added expense.

The 1' current signal I is applied to a peak pulse circuit 31 and to anR time base circuit 32 through weld current signal lines 34 and 35. Thepeak pulse circuit 31 produces a positive going peak pulse (lpp)beginning at the weld current amplitude maximum and applies same throughpeak pulse line 38 to a weld contact resistance (R) signal generatorcircuit 39. The peak pulse circuit provides a corresponding negativegoing pulse to the R time base circuit through a line 37.

The R time base circuit 32 provides a short time pulse (the III pulse)at the time of peak weld current amplitude, the duration of which isinversely proportional to the peak weld current amplitude, and appliessame through lines 42 and 41, respectively, to the R generator 39 and toa synch circuit 43. The R generator 39 is fed the voltage appearingacross the welding electrodes 14 through lines 46 and 47. In response tothese inputs, the R generator generates a pulse of amplitudeproportional to the weld contact resistancetthe R pulse) on line 49. Thesynch circuit 43 provides a short synch pulse, coincidental with peakingof the R pulse and of opposite sign, on synch line 51.

The weld termination unit 19 comprises an end ratio detector 56, fed bythe'R generator 39 and synch circuit 43 through lines 49 and 51,respectively. The end ratio detector normally provides an end ratiopulse on line 57 in response to a drop of the weld contact resistance toa preselected fraction, termed the end ratio, of its peak value. The endratio pulse line 57 drives an end weld circuit 59. When the weld contactresistance reaches the end ratio within a preselected time range, ashereinafter discussed, the end weld circuit 59 provides an end weldsignal on line 61 to the weld timer 12 for causing same to terminate theweld interval.

The weld terminating unit 19 further includes a plurality of timerscomprisinga high limit timer 63, an initial blanking timer 64, a lowlimit timer 67 with a low limit memory circuit 71 and a lockout timer68, for timing various periods within the weld'interval, as well asalarm circuitry 72 and a clamp and reset circuit 74 for controlling theactuation of the aforementioned timers as well as other portions of thecontrol 10. More particularly, the clamp and reset circuit 74 isprovided with a weld interval signal through a line 76 from the weldtimer 12. The clamp and reset circuit 74 provides clamping potentials attimes outside the weld interval through a clamp line 77 to theaforementioned timers 63, 64, 67 and 68 and also provides reset signalson a reset line 78 to the high limit timer 63, low limit memory 71 andlockout timer 67. Extensions 77a and 77b ofthe clamp line 77 supplyclamp signals to the R generator 39 and end ratio detector 56 to preventtheir operation outside the weld interval. Portions of thealarm circuit72 are responsive to the high limit timer 63, low limit memory 7 I andlockout timer 68 as indicated schematically by the broken line 81.

Considering the connections of timers 63, 64, 66 and 67 to otherportions of the control 10, the initial blanking timer 64 provides anoutput on an initial blanking line 84 to the peak pulse circuit 31 tobar operation thereof during the initial unstable resistance portion ofthe weld interval. The low limit timer 67 signals the end of the lowlimit period through a line 86 to the low limit memory 71 and through aline to the end weld circuit 59. The low limit memory 71 is supplied tothe end ratio pulse by an extension 570 of the end ratio line 57. Shouldthe end ratio occur before the end of the low limit period, the lowlimit memory 71 provides an output on a line 87 to the end weld circuit59 for causing weld termination at the end of the low limit period. Thelockout timer 67 signals the end of the lockout interval through a line88 to the end weld circuit 59 to cause the weld to be then terminated ifthe end weld circuit has not previously done so.

Unless otherwise noted, the transistors in the circuitry describedhereinafter are for purpose of convenience illustrated as NPN types.However, it will be apparent that the control embodying the invention isreadily adapted to use with components of opposite polarity to thatshown, if desired.

RESISTANCE SENSING UNIT IS The resistance sensing unit 18 (FIG. 2)provides an output signal I representational of the weld currentwaveform. The air core coil 26 has a current balance potentiometer I02connected thereacross. The armature I03 of said potentiometer connectsthrough a resistor IR to the input terminal I06 of theintegrator-amplifier 28 for applying a signal (dl/dt) theretoproportional to the time rate of change of weld current. A Zener diodeIZE is connected at its anode to the reference potential line 23 and atits cathode through a series resistor 6R and diode IRE to the positivepotential line 22 so that the upper or cathode end of the Zener remainsat a constant potential intermediate those of lines 23 and 22, hereabout 12 volts positive. One end of the air core coil 10! is connectedthrough a resistor 2R and Zener diode lZE to the reference line 23.

The amplifier 28 is a high gain phase inverting DC amplifier comprisingtransistors lQ-6Q. Transistors IQ and 20 are connected as a doubleemitter follower, the emitter of transistor 10 being connected to thebase of transistor 20. The base of transistor 10 directly connects tothe input terminal 106. The collectors of transistors 10 and 20 connectdirectly to the positive potential line 22. The emitter of transistor 20connects through resistor 3R to the reference line 23. The doubleemitter follower IO, 20 reduces the current drawn by the amplifier 10-60from the air core coil l0l to a negligible level.

Transistors 3Q and 40 are also connected as a double emitter follower,the emitter of transistor 40 being connected to the base of transistor30. i

The collectors of transistors 30 and 40 connect, the former through aresistor 4R, to the positive potential line 22. The emitter oftransistor 30 connected to the emitter of aforementioned transistor 20.The base of transistor 40 connects to the upper end of Zener diode IZEand is held thereby at a constant positive potential. As a result,transistor 40 conducts at a constant rate through the base-emitterjunction of transistor 30 whereby the current flow through transistor 30and voltage drop across resistor 4R are linearly related to the emittersignal of transistor 20. Thus, the collector signal of transistor 30 isa linear representation of the input signal at input point 106.

Amplifier transistor 50 is a PNP type connected at its emitter throughthe aforementioned diode IRE to the positive potential line 22 and atits collector through a resistor 9R to the reference line 23. Thebase-collector junction thereof is bypassed by a series resistor 7R andcapacitor 3C. The collector signal of the transistor 30 is applied tothe base of transistor 50 which provides a phase inverted and amplifiedoutput at its collector.

Transistor 60 comprises an emitter follower output stage, its collectorbeing directly connected to the positive potential line 22 and itsemitter being connected through series resistors 10R and HR to thereference line 23. A calibration resistor lCL parallels resistor "R. Acapacitor 27C parallels said resistors. The output ofamplifier-integrator 28 appears on line 34 connected to the emitter oftransistor 60. Asa result of the phase inversion accomplished byamplifier transistor 50, a positive going input to the input terminal106 will result in a negative going output on line 34.

A signal feedback path 111 is provided between the output and input ofthe amplifier-integrator 28 and, in conjunction with the amplifier 10-60integrates the dl/dr signal input to achieve the output signal Icorresponding in waveform to the weld current. The feedback path Illcomprises a capacitor lC connected between the output line 34 and inputterminal 106. 1

In addition, a DC feedback path generally indicated at 112 is providedto achieve long term stability by reducing the gain of the amplifierlQ-6Q for DC conditions and to establish a stable operating point. TheDC feedback path 112 is arranged to hold the resting voltage for theamplifier output at approximately that of the Zener IZE. The feedbackpath "2 comprises series resistors 5R and 8R connected between the inputterminal I06 of the amplifier and a point "3 intermediate output emitterresistors l0R and HR above mentioned. In addition, a relatively largecapacitor 2C connects from a point 4 intermediate the DC feedbackresistors SR and 8R to the upper end of Zener diode IZE. Capacitor 27improves stability by shunting transients appearing on the output line34 to the reference line 23.

PEAK PULSE CIRCUIT 31 The peak pulse circuit 3! detects the point ineach cycle of weld current at which the peak weld current amplitude,here the positive peak, occurs and comprises transistors 70 through [00.

Transistors 70 and comprise a trigger circuit. Transistor 8Q isconnectedat its collector through a resistor 16R to the positive potential line22 and at its emitter through series voltage dropping diodcs 5RE andISRE and line 116 to the upper end of aforementioned Zener IZE. Aresistor 17R connects from the positive potential line 22 to the emitterof transistor 80 and operates in conjunction with diodes SRE and 6RE andZener lZE to stabilize the emitter potential of transistor 80. Theinitial blanking line 84 connects through a series resistor lSR anddiode 4RE to the base of transistor 80 to apply a positive potentialthereto during initial blanking period so as to maintain sameconductive. The base of transistor 80 is also connected through a seriesresistor 14R and diode 3RE to the output line 34 of the integratorcircuit 38 so as to conduct in response to a rising l signal conductedthrough diode 3RE.

Transistor 70 is connected at its collector between resistor 14R anddiode 3RE and is connected at its emitter through the line 6 to theupper end of the Zener lZE. When the transistor 70 is conductive, itblocks diode 3RE and thus prevents transistor 80 from responding to arising l signal on the line 34. A capacitor 4C couples the base oftransistor 70 to line 34 and charges while the 1 signal on line 34 ispositive going, the charging current going to the base of transistor 70to render same conductive while the capacitor 4C is charging. A biasresistor 13R connects between the base and emitter of transistor 70. Adiode 2Re parallels said resistor 13R and is oriented with its cathodetoward capacitor 4C for discharging same. A series capacitor 5C andresistor 12R connect the collector of transistor 80 to the base oftransistor 70 for coupling a negative pulse to the base of transistor 70upon conduction of transistor 80 to insure complete and rapid blockingof transistor 70 at the peak of the weld current and corresponding lsignal waveforms and hence insuring rapid and complete conduction oftransistor 80.

The collector of transistor 80 is connected through a series couplingcapacitor 6C and resistor 18R to the base of input transistor of theone-shot circuit 90, for coupling thereto a negative pulse uponconduction of the trigger transistor 8Q at the weld current peakamplitude.

The one shot circuit 90, 100 includes dropping resistors 20R and 24Rwhich couple the collectors of transistors 90 and 100, respectively, tothe positive potential line 22. The emitters of said transistors areconnected directly to the reference potential line 23. Base bias isprovided the transistors 90, 100 by bias resistors 19R and 23R,respectively, connected to the reference line 23. A resistor 21Rconnects the collector of transistor 100 to the base of transistor 90.Series capacitor 7C and resistor 22R connect the collector of transistor90 to the base of transistor 100. The peak pulse line 38 to the Rgenerator 39 (FIG. I) connects to the anode of a clamping diode 50RE,the cathode of which connects to the collector of transistor 90. Thetransistor 90 is normally conductive for drawing clamping currentthrough the line 38, but is blocked at the l signal peak by the trigger7Q, 80 for a period of length determined by the RC time constant ofcapacitor 7C and resistor 22R, the positive peak pulse lpp thcnappearing on the collector of transistor 90 for unclumping line 38. Line37 connects the collector of normally blocked transistor I to the R timebase circuit and impresses a negative going pulse thereon during thepositive peak pulse lpp on line 38.

R TIME BASE CIRCUIT 32 The R time base circuit comprises transistors IIQthrough 150 produces a l/I pulse of width inversely proportional to weldcurrent amplitude.

Transistor IIQ connects at its collector through a series resistor 25Rand diode 7RE to the full wave potential line 24 and at its emitterthrough a resistor 27R and aforementioned line 116 to the'upper end ofZener diode IZE in the amplifier-integrator circuit 28. A calibrationresistor 2CL parallels resistor 27R. The weld current signal I from theoutput line 34 of the amplifier-integrator circuit 38 is coupled throughline 35 to the base of transistor 110. As a result of the regenerativeaction of resistor 27R, transistor IIQ conducts collector curthrough aresistor 26R to the full wave rectified line 24 and its collectorconnected through a series capacitor 8C and resistor 28R to thereference line 23. A diode 8RE is connected across the resistor 28R withits cathode toward the reference line 23.

The base of transistor 120 is driven from the collector of transistorI10 and, due to the degenerative action of resistor 26R, tra nsistor.120 also provides a collector current propor-' tional to the weldcurrent signal I during positive half cycles thereof for chargingcapacitor 8 C. i

TransistorI3Q is a unijunction transistor having its upper, baseconnected through a resistor 29R to the positive potential line 22 andits lower .base connected directly to the reference line. 23. Theemitter of unijunction I30 is, connected to the upper plate of capacitor8C a sufficient charge thereon causing unijunction 130 to conduct, gTransistors I and ISO comprise a flip-flop circuit. ,The collectors oftransistors I40 and I50 connect through respective resistors 33R and 36Rto the positive potential line 22 and the emitters thereof connectdirectly to the reference line 23. Base bias is provided the transistors140 and 150 through bias resistors 32R and 37R, respectively, whichconnect to the reference line 23. A resistor 34R couples the base oftransistor ISO to the collector of transistor I40 and a resistor 35Rcouples the base of transistor 140 to the collector of transistor ISQ. Aseries clamping diode 9R5 and resistor30R connect the upper plate ofcapacitor BC to the collector of transistor 140 to normally clamp thecapacitor 8C at a low charge level insufficient to fire unijunction 130.The negative going pulse due to blocking of transistor I00 at thepositive weld current peak is coupled from line 37 through a capacitor26C and seclamp and reset circuit 74 (FIG. I), the anode of diode SIRE(FIG. 2) being connected to the collector of flip-flop transistor 140 toprevent charging of capacitor 8C outside the weld interval. The anode ofclamping diode SIRE also connects to the line 42 to the R generatorcircuit 39 for clamping said line at a low potential outside the weldinterval. The line 42 also connects to the collector of transistor I40to couple the positive l/l pulse, appearing on said collector whentransistor I40 blocks, to the R generator circuit as one output of the Rtime base circuit. Aforementioned line 4I connects the collector oftransistor ISO to the synch circuit 43 to provide a negative going pulsethereto at the time ofthe l/l pulse, as the second output of the R timebase circuit 32.

SYNCH CIRCUIT 43 The synch circuit 43 comprises transistors I and I70connected as a trigger circuit to produce a negative going synch pulseimmediately following the ill pulse. Transistor I60 is connected at itscollector through a resistor 42R to the positive potential line 22 andat its emitter through a resistor 4IR to the reference line 23.Transistor I70 is connected at its collector directly to the positivepotential line 22 and at its emitter through a resistor 43R and thencein series through the aforementioned resistor 41R to the reference line23. A capacitor IOC is connected through at its upper end through aresistor 39R to the positive potential line 32 and at its lower endthrough a resistor 40R to the reference line 23. The base of normallynonconductive transistor I60 connects between the capacitor IOC andresistor 14R. A clamping diode IORE connects at its anode to the upperplate of capacitor 10C and at'its cathode to the output line 41 of the Rtime base circuit 32. Thus, when the R time base flip-flop I40, I50resets at the end of the III pulse, diode IORE blocks and capacitor 10Ccharges through resistor 39R and the base of normally nonconductivetransistor I60 turning same on 'briefly. The resultant collectorpotential drop of transistor I60 briefly blocks transistor [70,momentarily dropping the emitter potential thereof to form a'negativegoing synch pulse which is taken from said emitter through the line 51and applied to the end ratio detector 56 (FIG. I).

R GENERATOR CIRCUIT 39 The R generator 39 (FIG. 3) provides an R pulseoutput for each weld current cycle following'the initial blankingperiod, which 'R pulse-is, proportional in amplitude to thecontemporaneous value of the weld contact resistance. The electrodevoltage lines 46 and 47 (FIG. I connected across the welding electrodes14 are bridged by a potentiometer 119 (FIG. 3). Lines 121 and 122connect the armature 123 and one end of the potentiometer 119 to theprimary winding I24 ofa transformer IT. The center tapped secondarywinding 126 of transformer IT is connected at its ends through diodesIIRE and IZRE to a common output point I27 to define a full waverectifier. The center tap I28 of secondary winding I26 is connectedintermediate the ends of a resistive voltage divider comprising seriesresistors 44R and45R connected between the positive potential line 22and reference line 23 for determining the voltage level of point 127under conditions of zero electrode voltage. A small capacitor 25Cconnects the point 127 to an extension 23d ofthe reference line 23.

The R generator 39 further includes transistors I and I90. TransistorI80 connects at its collector through a series resistor 49R and diodeI3RE to the full wave source line 24, the diode I3RE being oriented topass current to said transistor. The emitter of transistor I80 connectsthrough regenerative resistor 47R to the reference line 23. Bias isapplied to the base of transistor I8Qthrough a resistor 143R connectedto the reference line 23. The rectified electrode voltage signal E isapplied from the point I27 directly to the base of transistor I80.

Transistor I is a PNP type and connects at its emitter through aregenerative resistor 50R to the full wave supply line 24. The collectorthereof connects through a series diode ISRE storage capacitor 11C tothe reference line 23. The diode ISRE is oriented to pass current fromthe collector of transistor 190 to storage capacitor C. Transistors I80and 190 are arranged so that the current output of the latter isproportional to instantaneous value of the full wave rectified electrodevoltage signal E at point I27. Transistors I80 and 190 thus operate in amanner analogous to the aforementioned transistors HQ and 120 of the Rtime base circuit 32. Thus, transistor I90 is capable of chargingstorage capacitor "C at a rate proportional to the instantaneous valueof the fully rectified electrode voltage signal E. I I

The collector of transistor I90 connects through a clamping diode I4REto the III pulse line 42 from the R time base circuit 32 (FIG. 2) fornormally clamping the anode of diode I5RE (FIG. 3) at a low potential toprevent charging of storage capacitor "C therethrough. The peak pulseline 38 from the peak pulse circuit 3| (FIG. 2) connects to the upperplate of storage capacitor 11C (FIG. 3) for normally clamping same at alow potential except during the peak pulse lpp immediately following aweld current amplitude peak. Thus, storage capacitor "C can support acharge only during the peak pulse lpp, is actually charged only duringthe ill pulse and is charged at a rate proportional to the instantaneousamplitude of the weld electrode voltage occuring during the chargingtime, whereby the maximum charge potential R across the storagecapacitor C is proportional to the contact resistance across the weldingposition.

Transistors 200 and 210 are connected as a Darlington pair forreproducing the R pulse appearing on capacitor "C with a small currentsupply capability and without discharging the capacitor "C. Thecollectors of transistors 200 and 210 directly connect to the positivepotential line 22. The base of transistor 200 connects through a portionof the line 38 to the upper plate of capacitor "C and the emitterthereof drives the base of transistor 210. The emitter of transistor 210is resistively connected to the reference line 23 by the end ratiooutput line 49 in series with means described hereinafter with respectto the end ratio detector 56 and the R pulse appearing on the emitter oftransistor 2lQ.

END RATIO DETECTOR 56 The end ratio detector 56 detects when the weldcontact resistance has peaked and decreased to a lesser preselectedvalue, the end ratio. The end ratio detector 56 comprises transistors220 and 230. Transistor 220 is a unijunction transistor, the lower baseof which is connected to the reference line 23 and the upper base ofwhich is connected through an isolating diode l6RE to the output line 49of the R generator 39. Diode l6RE is oriented for current flow from theoutput of the R generator to the upper base of the unijunction 220. Adiode l9RE connects the synch line 5| to the upper base of unijunction220 and, in the absence ofa synch pulse, applies a positive potentialthereto.

A series resistor 51R and diode RE are connected between the positivepotential line 22 and the reference line 23. The diode 20RE is orientedfor conduction through said resistor to the reference line so that theanode thereof remains above reference potential. A voltage dividercomprising a resistor 54R, a potentiometer 131 and a further resistor55R connects between the emitter of R generator Darlington transistor210 and the anode of diode 20RE. The armature 132 of potentiometer 13],connects to the anode of diode l8RE and therethrough to the emitter ofunijunction 220 as well as to a storage capacitor 12C connected betweenthe emitter of unijunction 220 and the base of output transistor 230.The armature 132 is adjustable to apply a preselected amplitude fractionof the R pulse to the storage capacitor 12C.

The extension 77b of clamp line 77 from the clamp and reset circuit 74(FIG. 1) connects through a resistor 56R (FIG. 3) to the cathode of aclamping diode 17RE and through said diode to a junction point 133intermediate the emitter of unijunction 220 and storage capacitor 12C.The low potential appearing on the clamping line 77b at times outsidethe weld interval prevents charging of the capacitor 12C.

End ratio output transistor 230 is connected at its collector through aresistor 58R to the positive potential line 22 and at its emitterdirectly to the reference line 23. The base of transistor 230 isnormally biased for conduction by connection intermediate the ends of aresistive voltage divider comprising serics resistors 57R and 59R. Saidvoltage divider is connected between the positive potential line 22 andthe reference line 23.

Thus, the storage capacitor 12C charges to a maximum level correspondingto the peak of the contact resistance amplitude and holds that charge asthe contact resistance amplitude diminishes during welding. During eachsynch pulse, the upper base of unijunction 220 carries the R pulseoutput of the R generator 39. As the R pulses diminish in amplitude,following the diminishing contact resistance as the weld nugget forms,the end ratio is eventually reached whereat the unijunction 220 fires,discharging the storage capacitor 12C therethrough to apply a negativegoing pulse to the base of transistor 230 to block same. This results ina positive end ratio pulse on the collector of transistor 230. The endratio line 57 connects to the collector of transistor 230 and thuscarries the end ratio pulse to the end weld circuit 59 and through theextension 57a to the low limit memory 7].

END WELD CIRCUIT 59 End weld circuit 59 comprises transistors 360through 39kQ and provides an end weld pulse to the weld timer 12 toterminate the weld interval. Normally conductive input transistor 360 isconnected at its collector through a resistor [HR to positive potentialline 22 and at its emitter directly to a secondary reference line 136from the clamp and reset circuit 74. The secondary reference line 136 isheld by diodes, hereinafter described, at a constant potential slightlyabove that of the reference line 23. The DC bias level on the secondaryreference line 136 is provided to insure the stability of the variousclamps, timers and other circuitry connected thereto. Base bias issupplied to transistor 360 through a resistor 109R connected to thereference line 23 whereby the base of said transistor normallymaintained at a potential below that of its emitter to insurenonconduction in the absence of positive base inputs.

Three sources of positive inputs connect to the base of transistor 560.More particularly, the end ratio pulse line 57 connects through aresistor 110R to the base of transistor 360. Further, line 88 from thelockout timer 66 and line 87 from the low limit memory 7] connect to thebase of transistor 360. Thus, a positive input from any one of thesethree circuits will render input transistor 36Q conductive.

Transistors 370 and 380 comprise a trigger circuit. Normally conductivetransistor 370 has its collector connected to the positive potentialline 22 through a resistor ll7R and its emitter connected through aresistor 118R to the reference line 23. Normally nonconductivetransistor 380 has its collector connected directly to positivepotential line 22 and its emitter connected through a resistor 119R tothe emitter of transistor 370 and thence through aforementioned resistor8R to the reference line 23. The base of transistor 38Q connectsdirectly to the collector of transmitter 370. 37Q. Conductive base biasis applied to transistor 370 by a series resistive voltage dividercomprising a resistor 116R connected from the positive potential line 22to the base of transistor 370, a resistor 114R connected from said baseto the emitter of said transistor and the aforementioned resistor 114R.The base of transistor 37Q connects to a junction point 138 through aseries resistor 115R and capacitor 20C. A resistor 113R connects thejunction point 138 to the reference line 23. The capacitor 20C is fullychargeable through the resistors 116R, SR and 113R in the absence of apositive potential on junction point 138.

A diode 4lRE connects the junction point 138 to the collector oftransistor 360 and is oriented to apply positive collector potential tosaid junction point. The line 85 from the output of the low limit timerconnects to the junction point I38 for applying a positive potentialthereto prior to the end of the low limit time period. The junctionpoint I38 is connected by a Zener diode ZZE to the secondary referenceline 136. The Zener 22E limits the voltage which may be applied at thejunction point I38 to the lower plate of capacitor 20C to a valueintermediate that of the secondary reference line I36 and the positivepotential line 22, here to 7 volts above the secondary reference lineI36, and thereby limits the charge on capacitor 20C when a positivepotential is applied tojunction point I38.

Thus, when one of the line 85 and collector of transistor 360 is at alow potential, the drop of the other to a low potential causes capacitor20C to transmit a negative going pulse to the base of transistor 370 toblock same and cause a high potential to appear on the emitter oftransistor 38Q.as the result of the consequent conduction thereof.

A feedback resistor 120R connects from the emitter of transistor 38Qback to the base of transistor 360 to hold same conductive untilcapacitor 20C charges fully or until the low limit timer resets to againrender line 85 positive, whichever The output transistor 390 of the endweld circuit is connected at its collector directly to positivepotential line 22 and at its emitter through a resistor 122R and seriesresistor 123R to the secondary reference line I36. The emitter oftransistor 380 connects the to base of transistor 390 through a resistor121R, the latter conducting in response to conduction of the former toprovide the positive end weld pulse. Transistor 390 l is connected as anemitter follower. The end weld line 61 connects from an output point I39intermediate emitter resistors 123R and 122R for coupling the end ratiopulse on the emitter of transistor 390 to the weld timer I2 for endingthe weld interval.

CLAMP AND RESET CIRCUIT 74 The clamp and reset circuit 74 provides clampand reset signals to the remainder of the control I and includestransistors 240, 250 and 260. Transistors 240 and 250 comprise a triggercircuit similar in operation and in circuitry to corresponding triggercircuits 300, 310 and 320, 330

hereinafter described with respect to the initial blanking timertransistor 240, at its collector directly to the positive potential line22 and at its emitter through a resistor 66R to the emitter oftransistor'24Q. A diode 23RE connects the emitter of transistor 250 tothe collector of transistor 240 to assist rapid switching of the trigger240, 250 to its energized state by conduction from said emitter to saidcollector. A voltage divider comprising series resistor 61R, diode 22RE,resistor 62R and resistor 63R is connected from the positive potentialline 22 to the reference line 23. The base of transistor 240 connectsbetween the resistors 62R and 63R which, when the diode 22RE isconductive, drives transistor 240 conductive. A filter capacitor 13C isconnected in parallel with the resistors 62R and 63R to preventapplication of transient voltages to the base of transistor 240. Theweld interval signal line 76 from the weld timer 12 connects through aseries resistor 60R and clamping diode'2lRE to a point 141 between theresistor 61R and diode 22RE. The weld timer l2 normally applies a low,clamping potential through line 76, resistor 60R and diode ZIRE to theanode of diode 22RE for blocking same and thereby blocking triggertransistor 240. During the weld interval, however, a high positivepotential, the weld interval signal, appears on line 76 to unclamp thediode 22RE and allow it apply positive base drive to the triggertransistor 240 for energizing the trigger circuit 240, 250.

The output of trigger circuit 240, 250 appears on the emitter oftransistor 250 and controls the output on clamp line 77 and reset line78.

More particularly, clamp transistor 260 connects at its collectorthrough a resistor 69R to the positive potential line 22 and at itsemitter through a series pair of voltage dropping diodes ZSRI'I and26Rl-I to the reference line 23. Base bias is supplied the transistor260 through a resistor 27R connected to the reference line 23. A signalresistor 68R connects the base of clamp transistor 260 to the emitter oftrigger output transistor 250 for rendering the clamp transistor, thenegative going potential appearing at the output of the trigger circuit240, 250 at the beginning of weld interval thus blocking clamptransistor 260 and removing the low, clamping potential from thecollector thereof. The collector of clamp transistor 260 connectsdirectly to the clamp line 77 and therethrough, as above described, tothe several timers 63, 64, 67 and 68.

The reset portion of the clamp and reset circuit 74 comprises a resistor7IR connected from the positive potential line 22 through couplingcapacitor 14C and diode 27RE in series to the reference line 23. Resetline 78 is connected between the lower end of capacitor 14C and diode27RE. A capacitor 28C connects the reset line 78 to the reference line23 for controlling switching transients on the reset line. A clampingdiode 24RE connects the upper end of capacitor 14C to the emitter oftrigger output transistor 250 for dropping the potential thereof inresponse to the emitter potential drop of transistor 250 at thebeginning of the weld interval and for causing the capacitor 14C toapply a negative pulse-to the reset line 78. I r

In addition, means are provided for manually energizing the reset line78. More particularly, a manually closable reset switch I43 is'connectedat one terminal to the reference line 23 and at its other terminalthrough a resistor 70R to the positive potential line 22. A clampingdiode 28RE is connected at its anode to the upper end of capacitor 14Cand at its cathode intermediate the reset switch 143 and resistor 70R.Thus, closure of the switch I43 causes the clamping diode 28RE to clampthe upper plate of capacitor 14C to reference level and thus, in amanner analogous to the action of the diode 24RE above described, causessaid capacitor to apply a negative going reset pulse to reset line 73.

The secondary reference line 136 is connected through the diodes 25REand 26RE to the reference line 23.

HIGH LIMIT TIMER 63 The high limit timer 63 provides an alarm at the endof the high limit period and includes a unijunction transistor 270 and aflip-flop circuit comprising transistors 280 and 290. A series timingpath comprising adjustable timing potentiometers I46 and I47, a fixedresistor 72R and a timing capacitor 15C is connected between a timingpotential supply line I48 and the reference line 23. More particularlythe armature ISI oftiming potentiometer I46 connects to the timingsupply line 148, the resistance winding thereof connects to the timingsupply line I48, the resistance winding thereof connects in turn to thearmature 152 of timing potentiometer I47 and the resistance winding ofthe latter connects to the fixed resistor 72R. The timing potential line148 in the present embodiment connects directly to the positivepotential line 22. The upper end of timing capacitor 15C connects to theemitter of unijunction 270 and through a series resistor 73R andclamping diode 29RE to the clamp line 77 whereby the timing capacitor[SC is clamped, except during the weld interval. at a low potentialinsufficient to fire the unijunction 270.

The unijunction 270 is connected at its upper base through a resistor74R to the positive potential line 22 and at its lower base through aseries diode 31RE and resistor 78R to the reference line 23. the diodeJIRI; being oriented to pass current from the unijunction to thereference line. The output of the unijunction 270 is taken at a pointI53 between said diode and resistor.

The flip-flop 280, 290 is energizable by conduction of the unijunction270 at the end of the high limit interval for actuating an alarm relaycoil I54. Normally blocked flip-flop transistor 280 connects at itscollector through relay coil I54 to a relay supply line I56. The lineI56 is normally connected by a switch, hereinafter described, to thepositive potential line 22. The emitter of flip-flop transistor 280connects to the secondary reference line I36. Normally conductiveflip-flop transistor 290 is connected at its collector through aresistor 83R to the positive potential line 22 and at its emitterdirectly to the secondary reference line I36. The base of flip-floptransistor 280 connects through a resistorBZR to the collector offlip-flop transistor 290. The base of flip-flop transistor 290 connectsto the collector of flip-flop transistor 280 through a resistor 8IR.Base bias is applied to flip-flop transistor 590 through a resistor 84Rconnected to the reference line 23. The base of flip-flop transistor 280is connected to the reset line 78 through a network comprising a seriescapacitor 16C and resistor 79R, both paralleled by a further resistor88R whereby a negative pulse on the reset line 78 will reset theflip-flop 28, 290 to its normal state.

Firing of the unijunction 270 causes conduction of flip-flop transistor280 by means of series resistor 77R and diode 32RE connected from theunijunction output point I53 to the base of flip-flop transistor 280. Aseries clamping diode MR and resistor 75R connect between the upperplate of capacitor C and the collector of transistor 280 wherebyconduction of said transistor 28Q prevents recharging of "the timingcapacitor ISC. A diode 33RE connects at its anode to the collector oftransistor 280 and at its emitter to the positive potential line 22 toprevent a rise in collector potential above the potential of positiveline 22 due to transients generated by the relay coil 154. v

INITIAL BLANKING TIMER 64 The initial blanking timer 64 holds the peakpulse circuit 3] inoperative except during the portion of the weldinterval following the initial blanking period and comprises a triggercircuit incorporating transistors 300 and 310. A timing line clamp line77 for holding the timing capacitor discharged except during the weldinterval. The upper end of capacitor I7C is also connected through aseries diode 35RE and resistor 87R to the base of normally blockedtransistor 300 for rendering same conductive at the end of the initialblanking period due to a sufficient charge on said timing capacitor.

Transistor 300 is connected at its collector through a resistor 137R tothe positive potential line 22 and at its emitter through a resistor 89Rto the reference. line 23. The emitterbase junction of transistor 300 isshunted by a relatively large resistor 88R. The transistor 3IQ connectsat its collector directly to the positive potential line 22 and at itsemitter through a resistor 90R to the emitter of transistor 300. Outputis taken from the emitter of normally conductive transistor 310 on theinitial blanking line 84 connected thereto.

LOW LIMIT TIMER 67 The low limit timer 67 provides outputs to the endweld and low limit memory circuits 59 and 71, respectively, at'the endof the low limit period. The low limit timer 67 is similar in circuitryto the initial blanking timer 64 differing therefrom only in theclamping and timing circuitry associated with its timing capacitor.Thus, the low limit timer comprises a trigger circuit includingtransistors 320 and 330 and associated resistors 93R97R, timingcapacitor I8C and diode 37RE corresponding to and interconnected andconnected to lines 22, I36 and 23 in the same way as transistors 300,310, resistors 87R-90R and 137R, timing capacitorl7C and diode 35RE,respectively, of the initial blanking timer 64 above described. Thus,further description of said corresponding parts of trigger 320, 330 isnot believed required.

With respect to the clamping and timing current supply circuitry of thelow limit timer, timing current is supplied to the upper plate of timingcapacitor [8C through a series resistive line comprising timingpotcntiometers I62 and I63, fixed resistor 92R and further fixedresistor 9IR. The armature I64 of potentiometer I62 connects to thetiming potential line I48, the armature I65 of potentiometer I63connects to the resistive element of potentiometer I62 and the resistiveelement of potentiometer I63 connects to aforementioned resistor 92R.

The clamping line 77 connects to the cathode ofa clamping diode 36RE andtherethrough to a point between resistors MR and 92R to prevent chargingof timing capacitor 18C to a level sufficient to activate the triggercircuit 320, 330, except during the weld interval.

Considering the output circuitry of trigger circuit 320, 330, theemitter of transistor 330 connects to the secondary reference line I36through a resistive voltage divider comprising series resistors 99R and100R. The output ofthe low limit timer is taken from a pointintermediate said resistors from which an isolating diode 42RE connectsto the low limit line for conduction of current to the end weld circuit59. Output is also taken from the emitter of trigger output transistor330 through the output line 86 to the low limit memory circuit 7l. 1

LOW LIMIT MEMORY CIRCUIT 7I The low limit memory circuit 71 (FIG. 5)energizes an alarm and the end weld circuit in response to an end ratiocondition occuring during the low limit period and comprises transistors340 and 35Q connected as a flip-flop circuit. Two inputs are applied tothe low limit memory flip-flop 340, 350. More particularly, the lowlimit line 86 connects through aseries resistor 98, diode 39RE andresistor 101R to the base of normally blocked flip-flop transistor 340.The diode 39RE is oriented to pass current from the low limit timertoward the flip-flop transistor 340 when the low limit output transistor330 conducts prior to the end of the low limit period. However, as thesecond input, the end ratio line 57a from the end ratio detector 56connects through a clamping diode 38RE to the diode 39RE, said diodesbeing arranged anode to anode, for preventing the low limit timer forfiring the flip-flop transistor 340 except upon occurrence of an endratio pulse during the low limit period.

The remainder of the flip-flop 340, 350 is similar to the flip-flop 280,290 described above with respect to the high limit timer 63, thetransistors 340 and 350, resistors 102R- I06R and 108R, capacitor 19C,diode 40RE and alarm energizing relay coil 167 of the low limit memoryflip-flop 340, 350 corresponding to and being connected to each otherand to the lines I56, 22, 136, 78 and 23 in the same manner as thetransistors 280 and 290, resistors 79R-84R, capacitor 14C, diode 33REand relay coil I54, respectively, of the high limit flip-flop 280, 290.Thus, further description of said corresponding parts in flip-flop 340,350 is not believed required.

A positive output is taken from the collector of transistor 350 througha resistor 107R and, thence, through the low limit memory line 87 to theend weld circuit, upon energiza tion of the flip-flop 340, 350 inresponse to an end ratio pulse during the low limit interval.

LOCKOUT TIMER 68 The lockout timer 68 energizes an alarm and the endweld circuit at the end of the lockout period if an end ratio conditionhas not been previously reached. The lockout timer comprises aunijunction transistor 400 and a flip-flop circuit comprisingtransistors 410 and 420. The circuitry of the lockout timer 68 issimilar to that of the high limit timer 63. More par ticularly, theunijunction 400, transistors 410 and 420. resistors l25-I35R and 137R,diodes 43Rli-47RE, timing potentiometers l7] and I72, capacitors 21C and22C and alarm relay coil [76 of the lockout timer 68 correspond to andare connected to each other and to the lines 22, 23, 77, 78, I36, I48and I56 in the samemanner as the unijunction 270, transistors 280 and290, resistors 73R-75R and 77R-84R, diodes 29RE-33RE, potentiometers I46and 147, capacitors C and SC and relay coil I54, respectively, of thehigh limit timer 63. Further description of such corresponding parts ofthese two timing circuits is thus not believed required.

In addition, a resistor [36R is connected to the collector of flip-floptransistor 420 to provide a positive potential, at the end oflockoutperiod, through line 88 to the end weld circuit 59 to terminate the weldinterval if the weld interval has not already been terminated by an endratio condition. In the event that the weld time is terminated beforetiming out of the lockout timer, the clamp line 77 discharges the timingcapacitor 21C toprevent output from the lockout timer.

, FIG. 5 further discloses the connection of the line 77b to be theclamp line 77 adjacent resistor 125R of the lockout timer and a manuallyactuable switch 174 for connecting the alarm relay current line 156 tothe positive potential line 22.

' ALARM UNIT 72 AND POWER SUPPLY 21 Connected across a pair of AC sourcelines 178 and 179 are preferably identical alarm circuits 181-183responsive to timing out of the low limit timer 67, the high limit timer63 and the lockout timer 68, respectively. The low limit alarm circuitltlI'comprises an alann lamp 184 connected in series with a normallyopen contact 167a of the low limit relay 167 between the AC source linesI78 and I79. A resistor 160R parallels the lamp 185. Preferablyidentical alarm circuit 182 comprises a corresponding lamp 185, normallyopen contact 154a of high limit relay I54 and resistor 161R. Preferablyidentical alarm circuit I83 comprises a corresponding lamp 186, normallyopen relay contact 176a of lockout relay I76 and resistor 162R.

Low limit counter and high limit counter circuits I87 and 188 areconnected across the AC source lines I78 and I79. More particularly, lowlimit counter circuit 187 comprises a low limit counter I89 of anyconvenient type in series with a further normally open relay contactl67b of low limit relay 167 between the AC source lines of 178 and I79.The counter 189 is paralleled by a series resistor 163R and capacitor160C. Preferably identical high limit counter circuit 188 comprises acorresponding counter I90, relay contact l54b of high limit I relay 154,resistor 164R and capacitor 161C.

AC source lines 178 and 179 are connected to the ends of the primarywinding 19! of a main power transformer 192.

The secondary winding [93 of the main power transformer connect at itsends through diodes 48RE and 49RE to and through a resistor 138R to thehigh level input of a filter and voltage regulating circuit 194 of anyconvenient type as well as to the full wave, unfiltered supply line 124.The center tap 195 of the secondary winding 193 connects through thereference line 23 to and through the filter and voltage regulatingcircuit 194. The filter andvoltage regulating circuit I94 provides aconstant positive DC output on the positive line 22.

OPERATION Although the operation of this invention has been indicatedsomewhat above, the same will now be described in detail to insure acomplete understanding of the invention.

FIG. 8 discloses the change of the weld contact resistance with time atthe welding position during a weld. From the time t, at which weldcurrent is started until a time 1,, the contact resistance is unstable.Thereafter, it rises to a peak value at time I, and then falls at agenerally uniform rate. It has been found that the fall of the contactresistance is a reliable indicator of weld nugget formation. a

More particularly, there is a high degree of probability that a goodweld will have been made if the weld current is terminated when thecontact resistance has fallen to a preset fraction of its peak value,the end ratio. Further, it is desirable that the end ratio occur withina particular time range 1 -h, after the resistance peak inasmuch as toorapid or too slow a rate of resistance drop may result in inferior weldsdue to excessive or insufficient heat and, in addition, too slow aresistance drop may not permit completion of a weld within theproduction schedule.

RESISTANCE SENSING UNIT [8 The weld contact resistance sensing unit 18provides, by particularly advantageous method and means, the first broadrequirement of the control l0, that is, a signal R proportional to theinstantaneous weld contact resistance. i

lNTEGRATOR-AMPLIFIER CIRCUIT 28 In order to derive a reliable weldcontact resistance signal R, it is necessary to have a signal waveform(l) proportional to the weld current waveform. To this end, the air coresensing coil 26 is placed at a convenient location in the field treatedby the secondary current of the welding machine. Since the coupling isthrough air, the output of the coil 26 is proportional to the rate ofchange of weld current (dl/dt) as shown in FIG. 7a. The high gainamplifier lQ-6Q greatly amplifies any signal applied to the base oftransistor IQ as in output on the emitter of transistor 60 and, due tocircuit phasing, the output will be inverted in sign I out of phase)with respect to the input. Further, since transistors IQ and 20 areconnected as a doubleemitter follower, the base of transistor IQ willdraw negligible current from the signal source. The input signal isapplied to the amplifier lQ6Q from the air core coil 26 through seriesresistors IR and 2R and appears at the base 106 of transistor 10.

I An input signal voltage appearing at the base 106 of transistor 10appears at the emitter of transistor 20. This voltage signal isreproduced with high linearity at the collector of transistor 30 fromwhich sufficient current may be drawn (without requiring significantcurrent at the base of transistor 10) for driving amplifier transistor50. The output of transistor. 50 is taken from its collector, invertedin sign, appreciably amplified in magnitude and applied to emitterfollower output transistor 60, appearing at the emitter thereof andhence on output line 34.

The amplifier IQ-6Q has extremely high gain and the input terminal 106thereof must therefore be very near signal ground, that is, thepotential on the cathode of Zener lZE, if the amplifier is to operateproperly since, due to its high gain, an appreciably large input signalwould drive the amplifier beyond its limits.

Given the above considerations, there is therefore a current in thesignal feedback path through capacitor [C from the amplifier output toits input equal to and opposite in sign to the current created by theair core coil output signal applied to input resistors IR and 2R. Moreparticularly, any current created in these input resistors must flow onthrough the feed back capacitor 1C to the output terminal of theamplifier since the amplifier itself can draw no current withoutexceeding its linear range. Thus, a positive going signal appearing tothe input resistors causes the amplifier to produce a negative goingoutput which draws current through the feedback capacitor lC, whichcurrent must equalthe input current during linear operation of theamplifier.

Since the input signal applied by the air core coil 26 to the input 106of the amplifier is proportional to the time rate of change of the weldcurrent (dI/dt) and since the input path of the amplifier is resistive,the current in the input path is necessarily proportional to dl/ dt).The feedback path through capacitor 1C is capacitive and therefore thefeedback current thcrethrough will be the output voltage applied to thecapacitor, i.e., dV /dt, where V,, is the amplifier output voltage.Restated mathematically,

Thus, the output signal I (FIG. 7b) from the amplifier is proportionalto the welding current.

in order to gain long term stability, resistors SR and SR and capacitor2C form a DC feedback path to reduce the gain of the amplifier for DCconditions and to establish a stable operating point. The restingvoltage for the output line 34 of the amplifier is approximately that ofZener lZE which, in the particular embodiment shown, is approximately l2volts.

PEAK PULSE CIRCUIT 31 The peak pulse circuit 31 provides the peak pulselpp (FIGS. 7c and l) by switching at one peak of the weld currentwaveform in each current cycle, when the weld current waveform amplitudeis unchanging, that is, when dl/ d! is zero. It is at this point in theweld current waveform that the weld resistance is measured so since itis at this point that the electrode voltage E may be accurately readwithout error due to unintended pickup of a dl/ dt signal on theelectrode voltage sensing lines 121 and 122.

The weld current signal I on the output line 34 of theintegrator-amplifier 28 is applied to the base of transistor 70 throughcapacitor 4C. As long as the current signal I is increasing, saidcapacitor will be charged and the charging current therethrough willflow in the base of transistor 70 to hold same conducting. At the peakamplitude point oftheweld current waveform, the current signal I is nolonger increasing whereby charging current no longer flows in capacitor4C. As a result, transistor 70 blocks and no longer shunts thebaseemitterjunction of transistor 80. Thus, the current signal I on line34 is applied through resistor 14R and diode 3RE to the base oftransistor 80 at and following the peak in the weld current waveform torender the transistor 80 conductive. Transistor 80 remains conductivefor the duration of the positive half cycle weld current signal Iwaveform. When the current signal I swings negative, transistor 80 willreturn to its normal blocked condition.

The one shot circuit 90, 100 is arranged so that at all times in a weldcurrent signal I cycle, except during the brief period at and followingthe positive peak, transistor 90 conducts to clamp t .a line 38 to the Rgenerator 39 at a low potential to prevent operation thereof. Whentransistor 80 begins conduction at the peak of the weld currentwaveform, the resulting drop in potential on the collector thereof iscoupled as a negative going pulse through capacitor 6C to the base ofone shot transistor 90, causing same to block and hence causing one shottransistor 100 to conduct. Transistor [Q continues to conduct untileither capacitor l0C becomes charged by the base current in transistor100 or until transistor 80 blocks and renders transistor 90 againconductive. It is immaterial whether the one shot circuit 90, 100 timesitself out by full charging the capacitor 7C or is reset by blocking oftransistor 80 as long as the duration of blocking of transistor 90 is.

greater than I millisecond, which it will be in either case.

The positive pulse lpp appears on the collector of transistor 90 when itblocks at the peak of the weld current waveform, and is applied throughdiode SORE the peak pulse line 38 to the R generator 39, removing theclamp therefrom. Also at the peak of the positive weld current signal 1half cycle, the unblocking of transistor 10Q causes a negative goingpotential to appear on its collector which is applied through line 37and capacitor 26C to the R time base circuit 32 hereinafter described.

The above operation of the peak pulse circuit 31 applies between the endof the initial blanking period of the weld interval and the end of theweld interval. At all other times including the initial blanking period,during which the weld contact resistance is subject to instabilities, itis desired to prevent the R generator 39 from operating and fromproducing its R signal output. To this end, at all times except duringthe portion of the weld interval following the initial blanking period,the initial blanking timer 64 applies positive potential through line84, resistor [SR and diode 4R5 to the base of transistor for maintainingsame continuously conductive. This prevents switching of the transistor80 at the positive peak of the 1 signal waveform and hence prevents samefrom passing negative pulses to the base oftransistor 90. As a result,during the initial blanking period of the weld time and at all nonweldtimes transistor continuously conducts clamping current through the line38 from the R generator thereby maintaining the latter disabled.

R TIME BASE ClRCUl T 32 The R time base circuit 32 generates a positivepulse l/l (FIG. 7d) of width inversely proportional to weld current peakamplitude. One such l/l pulse is generated in each weld current cycleand begins, concurrently with the peak pulse lpp, at the amplitude peakof the positive l signal halfwave..

Transistor is driven through line 35 by the current signal I from theoutput of the integrator-amplifier 28. Because of the degenerativeaction of resistor 27R, the collector current of transistor H0 isproportional to the weld current, transistor llO conducting duringpositive going half cycles only of the l signal waveform. The collectorcurrent in transistor llQ creates a voltage drop across resistor 25Rwhich is also proportional to weld current, so that the collectorpotential of transistor "0 drops to its lowest value at the peakamplitude of the positive I signal halfwave. Base drive is supplied toPNP transistor from the collector of transistor 110. Due to thedegenerative action of resistor 26R, the collector current of transistor120 is also proportional to the weld current, transistor 120 conductingduring positive 1 signal halfwaves only.

Normally conductive flip-flop transistor 14Q normally shunts thecollector current of said transistor l2Q to the reference line 23through clamping diode 9RE and series resistor 30R thereby preventingtransistor 120 from charging the capacitor 8C.

However, at the peak of the positive 1 signal half cycle, one shottransistor 100 of the peak pulse circuit becomes conductive whereby alow potential appears on its collector and is coupled as a negativepulse through capacitor 26C and resistor 31R to the base of flip-floptransistor 14Q causing same to block and hence causing flip-floptransistor ISO to conduct. With transistor nonconductive, it no longershunts the capacitor 8C through diode 9RE and resistor 30R. As a result,the collector current of transistor I20 charges the capacitor 8C at arate proportional to the weld current amplitude, until its charge levelis sufficient to fire the unijunction I30. The firing of unijunction I30discharges capacitor 8C thcrethrough to couple a negative pulse throughcapacitor 9C and resistor 38R to the base of transistor ISO to blocksame and reset the flip-flop 140, 150. Thus, transistor 140 is restoredto conduction, dropping the collector potential thereof and terminatingthe HI pulse.

Considering in more detail the time duration of the positive l/l pulse,that is, the charging time of capacitor 8C, such time is constrained tobe relatively short so that charging will occur only while the currentsignal l is not changing appreciably in The formula for charging acapacitor with a constant current is: Y

' CV=it where C, the capacitance and V, the emitter voltage for firingthe unijunction 130 are constants and i, the charging current and t, thecharge time are variables. The above expression may be rewritten:

But i is proportional to weld current, i.e.,

where l,,, is the welding current and k, is a constant ofpropertionality. Thus,

r==CV/k,,l,,, or, r lqll where k, is'ano'ther constant equal to CV/k,,.Thus, the width of the positive l/I pulse appearing on'the collector 140is inversely proportional to the weld current peak amplitude. In theparticular embodiment of the invention shown, the working range of thispulse width is from approximately 100 to 400 microseconds.

With the production of the current signal I by the integrator-amplifiercircuit 28 and the production of the III pulse by the R time basecircuit 32 discussed above, attention is directed briefly to theinterrelated functions of the calibrating resistors lCL and 2CL of theformer and latter circuits, respectively. Adjustment of the firstcalibration resistor lCL established the DC level of the integratoroutput, or current signal I (with respect to the cathode of Zener lZE),so that conduction of transistor 110 of the R time base circuit isimpending when the current signal I is zero. The second calibration iscarried out by setting of the calibration resistor 2CL which establishesthe relation between the current signal I and thecha'rging current forcapacitor 8C, thus relating the durationof' the III pulseto the currentsignal I. These calibrations pulse is maintained inversely proportionalto the magnitude of I the current signal I over the usable or workingrange of the circuit, for example l/l pulse widths of from 100.10 400microseconds.

One output of the R time base circuit appears on the collectoroftransistor 140 and is coupled by line 42 to the R generator 39. Moreparticularly, the line 42 is normally clamped by conduction oftransistor 140. This clamp is removed while the positive l/l pulseappears on the collector of blocked transistor 140. The other output ofthe R time base circuit appears on the collector of transistor 500 andconsists of a negative going pulse corresponding in time to the positivel/l pulse and ap- SYNCH, cmcurr 4a The output of the synch circuit 43appearing on synch line 51 isa series of negative going pulse (FIG. 7!!)each beginning at the time of the maximum amplitude point'of an R pulsefrom the R generator 39 and being of lesser duration than such R pulse.More particularly, synch transistor 160 is normally blocking for lack ofbase drive due to the normal charged condition of capacitor 10C. Duringtheill pulse flip-flop transistor lSQ draws current through diode 10REfrom the resistor 39R to clamp the upper plate of capacitor 10C at arelatively low level and hence to discharge said capacitor. At the endof the III pulse, the collector of transistor I50 again swings positiveand causes the diode 10RE to block whereby the upper plate of capacitor10C assumes a high potential due to its connection through resistor 39Rto the positive potential line 22. The lower plate of said capacitorfollows the upper plate and applies a positive potential to the base oftransistor I60 causing same to conduct. Thereafter, the capacitor 10Ccharges through resistors 39R and 40R and the base potential ontransistor I60 diminishes blocking transistor I60 after a timedetermined by the RC time constant of said resistors and capacitor.Thus, at the end olthe l/l pulse, a positive pulse appears on the baseof transistor 1.60 for rendering same briefly conductive. I

The resulting low collector voltage of transistor I60 is reproduced atthe emitter of transistor [70 as a negative synch pulse which is appliedthrough line 51 to the end ratio detector 56.

R GENERATOR 39 The R generator 39 produces R pulses (FIGS. 7g and m) ofamplitude proportional to the instantaneous weld contact resistance. Theelectrode voltage appearing across the welding electrodes 14 is appliedacross electrode voltage lines 46 and 47. A spurious dl/dt signal(similar to FIG. 7a) normally is superimposed on the electrode voltagewaveform on lines 46 and 47 due to inductive pickup from the weldtransformer secondary circuit. An electrode voltage signal E (FIG. 7e)proportional ,to this composite voltage on lines 46 and 47 is applied bythe potentiometer 119 (FIG. 3)to' lines 121 and 122 and therethrough tothe primary of transformer IT, The signal E is full wave rectified bydiodes RE and IZRE and applied through junction point 127 to the base oftransistor 'oftransistor yl is shunted to reference line'23 through thediode MRE, l/ l line 42 and R time base flip-flop transistor Thecapacitor "C is normally held discharged through the diode ISRE, peakpulse line 38 and'collector of normally conductive one shot transistor90.

' At the peak of the'positive l signalhalf cycle the positive peak lppappearson the collector of one shot transistor 90 and removes the clampnormally applied to the upper plate of capacitor C to ready same forcharging. The clamp applied to the anode of diode 15RE is removed when Rtime base flipflop transistor [40 blocks at the peak of the positive Isignal half cycle. The diode ISRE remains unclamped for the period ofthe ill pulse, that is, for a timer inversely proportional to the peakamplitude of the weld current in that cycle. The period of during whichthe upper plate of capacitor C remains unclamped exceeds the maximumpossible duration of the HI pulse. The collector current of transistorthen passes through diode ISRE and capacitor "C to charge the latter ata rate determined by said collector current.

At the weld'current peak amplitude, dI/dt is zero and the signal E atsuch time, as indicated at E, in FIGS. 7: and f, and therefore, thecharging current in capacitor 11C, is proportional to the true electrodevoltage peak amplitude. Since the maximum duration of the ill pulse isvery short, the rate of charging of the capacitor "C remains at leastsubstantially proportional to the true electrode voltage peak amplitudethroughout the charging time thereof. The capacitor 11C is thus charged,at the weld current peak, at a rate proportional to the electrodevoltage peak magnitude and for a time inversely proportional to the weldcurrent peak amplitude. The formula for charging a capacitor is:

Where C, the capacitance is a constant, v is the voltage on thecapacitor, l is the charge current and r is the charge time, v, i and Ibeing variables. The above expression may be written v=itlC but sincethe charge current i is proportional to the welding electrode voltage El==k,E,,, where k. is proportionality constant, and:

r lm/l where k, is a proportionality constant, it must be true that atthe time that transistor I40 again conducts to stop the charging ofcapacitor 1 1C,

wUgElq/IC or v-k,0 lulu )lC Thus, by Ohms Law,

/(3R, showing that the voltage to which the capacitor is charge isproportional to the weld contact resistance R.

When the R time base flip-flop transistor I40 begins conduction again atthe end of its l/l pulse, the diode ISRE is again blocked by theresulting low clamping potential applied to its anode through the diodeMRE, line 42 and transistor 140. However, the capacitor 11C carrying theresistance signal Ras the charge potential thereacross does not at thistime discharge since the positive peak pulse lpp has not yet terminated.The resistance signal R thus remains stored on capacitor C and isapplied to the Darlington pair 200, 210, appearing at the emitter ofDarlington transistor 2lQ. The Darlington pair 200 and 210 applies the Rsignal with a small current capability to the end ratio detector 56without discharging the storage capacitor "C.

After a delay of at least i millisecond, the peak pulse one shottransistor 90 resumes conduction, terminating the positive peak pulseipp and once again clamping the upper plate of storage capacitor "C tothe reference potential through the line 38 and clamping diode 50RE toreturn said storage capacitor to its nonnal discharged state. The widthof the R pulse appearing on the emitter of Darlington transistor 210 isthus at least I millisecond and will be longer where the width ofthe IIIis less than its maximum.

Thus, an R pulse appears at the emitter of Darlington transistor 2lQonce in each cycle of the welding current between the end of the initialblanking period and the end of the weld interval and lags the positive Isignal amplitude peak by a very short time interval equal to the widthof the ill pulse.

WELD TERMlNATlNG UNIT 19 END RATIO DETECTOR 56 The end ratio detector 56detects the fact that the weld constant resistance, and hence the valueof the. R signal, has reached a peak value and decreased from that peakover a number of cycles of weld current to a lesser value, that is, tothat fraction of its peak value selected as the end ratio.

Normally nonconductive unijunction transistor 220 requires apredetermined relationship between the potentials on its upper base andits emitter before it will conduct. As shown in FIG. 70, the upper baseof unijunction 220 is normally held at a high potential and, when atthis high potential, the unijunction will not conduct regardlessof thepotential which the associated circuitry can apply to its emitter. Moreparticularly, normally conductive synch transistor 17Q applies, througha line 51 and diode 19RE, a normally high potential to the upper base ofunijunction transistor 220. This high potential is removed once in eachcycle of welding current between the end of the initial blanking periodand the end of the weld interval by the appearance of the negative goingsynch pulse on line 51 which occurs as above mentioned when the R pulseis fully established. The negative synch pulse on line 51 blocks thediode 19RE. As a result, the simultaneously occurring R pulse at theemitter of Darlington transistor 210, applied to the upper baseunijunction 220 through diode 16RE, determines the potential on saidbase during a synch pulse. Thus, the upper base of unijunction 220 will,during a synch pulse, be at a relatively high potential when the weldcontact resistance is at its peak value and will be at a lower potentialwhen the weld contact resistance has decreased from its peak value.

if the unijunction 220 is ever to fire it will be during the synch pulseof the weld current cycle during which the weld contact resistance hasdropped from its peak value to the end ratio.

The R pulses on the emitter of Darlington transistor 210 are alsoapplied to the series line comprising resistor 54R, potentiometer l3],resistor 55R and conductive diode ZORE whereby a constant fraction ofthe amplitude of each R pulse, determined by the setting of the armaturel32 of potentiometer i3], is applied through diode I8RE to the R peakstorage capacitor 12C for charging same to said fractional level throughthe resistor 59R, DC power supply and transistor 210. Thus, as the weldcontact resistance rises in the early part of the weld intervalfollowing the initial blanking period, a preselected fraction of eachcorresponding R pulse is applied to the R peak storage capacitor 12C,raising the charge level thereof. After the weld contact resistance haspeaked and begins to decline, the value stored in the R peak storagecapacitor 12C remains constant at the preselected fractional value ofthe R pulse amplitude corresponding to the weld contact resistance peak.

The potential (FIG 7a) seen by the emitter of unijunction 220 is thecharge potential appearing on the storage capacitor 12C. The circuitparameters are such that the unijunction 220 will never fire until theweld contact resistance has declined from its peak value to the endratio, at which time the corresponding R pulse amplitude applied to theupper base of unijunction 220 during a synch pulse is low enough toallow the capacitor 12C to fire the unijunction 220.

Examining this circuit quantitatively, the condition for firing aunijunction is:

ve=nVb, where Ve is the emitter voltage, n is the intrinsic standoffratio of the unijunction (a constant) and Vb, is the voltage applied tothe upper base of the unijunction. Considering the emitter voltagedesired for firing the unijunction,

Ve=K R where K; is the setting of potentiometer 131 (a constant for anyparticular weld) and R, is the highest value reached by R during theweld interval. Considering the value of the upper base potentialrequired for firing,

b =R. Therefore, the condition for firing unijunction 22Q becomes:

' KJRPPR and R=( 39),! indicating that the unijunction 220 will fireafter R has peaked and decreased by a fixed percentage depending uponthe setting of potentiometer 131. The calibration of the presentembodiment is such that the percentage decrease is adjustable fromapproximately l2 percent to 45 percent drop in R to fire the unijunction220.

Firing of the unijunction 220 couples a negative going pulse throughstorage capacitor 12C to the base of normally conductive transistor 230to cause same to block momentarily and thereby create a positive goingpulse on the collector thereof, such positive going pulse, the R pulse,being applied to the output lines 57 and 57a of the end ratio detector56 leading to the end weld circuit 59 and to the low limit memorycircuit 71, respectively.

It will be noted that unijunction 220 cannot be fired if the storagecapacitor 12C remains uncharged. Thus, to prevent any possibility offalse firing of the unijunction 220 and, hence, of a false end ratiopulse output, the emitter side of storage capacitor 12C is clamped atlow potential through clamping diodes l7RE, resistor 56R and theclamping line 77b from the clamp and reset circuit 74 at all timesoutside the weld interval, this low potential clamp being removed by theclamp and reset circuit during the weld interval.

END WELD CIRCUIT 59 The end weld circuit provides a pulse (FIG. 7p) tothe weld timer 12 to end the weld interval.

The normally nonconductive input transistor 360 of the end weld circuit59 conducts in response to any one of three possible positive inputs tothe base thereof. The desirable input is a positive pulse appliedthereto through the resistor [R from the end ratio detector indicatingthat the weld contact resistance has fallen to its end ratio. Anotherpossible inputis a positive potential applied to said base through line87 from the low limit memory circuit 7| which will occur is the endratio is reached prior to the end of the low limit period. The last ofthese inputs to the base of input transistor 360 is a positive potentialapplied thereto through line 88 from the lockout timer 68, which willoccur if the end ratio has not been reached prior to the end of thelockout period.

The next transistor in the end weld circuit, transistor 370 is nonnallymaintained conductive by base current flow from resistor 116R, thecapacitor C normally being held discharged so as not to interfere withconduction of transistor 370. More particularly, the upper plate ofcapacitor 20C is normally held at the base potential of transistor 370by connection thereto by resistor 115. The lower plate of capacitor 22Cis normally held at fixed value above the reference potential, limitedby the zener ZZE, as a result the normally high collector potential ofaforementioned transistor 360 applied thereto by diode 41E and/or asresult of the normally high potential applied thereto'through line 85,diode 42RE, resistor 9R and the emitter of normally conductive outputtransistor 330 of the low limit timer 67.

Thus, while either the low limit timer output line 85 or the collectorof transistor 360 remains at a highpotential, the transistor'37Q remainsconductive. In other words, diodes 41RE and RE. act as an OR gate toapply positive potential to the point 138 when either or both areconductive. Since the low limit timer output line 85 remains at a highpotential until the end of the low limit timer period, the transistor370 cannot be energized to cause an end weld pulse prior to the end ofthe low limit period, even if the weld contact resistance reaches itsend ratio and causes transistor 360 to conduct. Thus, it is only afterthe end of the low limit period that the transistor 370 will respond toconduction of transistor 360. I

When the transistor 360 is conductive at the end of the low limit periodor begins conduction thereafter, the diode 4lRE blocks and the lowerplate of capacitor 20C is immediately lowered in potential by resistor113R causing the capacitor 20C to transmit a negative going pulse to thebase of transistor 370 for blocking same. Capacitor 20C subsequentlycharges through the resistive lines "6R, 115R, 113R to terminate thenegative going pulse on base of transistor 370. The high collectorpotential of the blocked transistor 370 is applied to normally blockedtransistor 380 to render same conductive whereby said high collectorpotential appears at the emitter of transistor 380. The feedback,resistor 102R applies such to the high emitter potential of transistor380 back to the base of transistor 360 to maintain same conductive for ashort period determined by the charge rate of capacitor 20C. The highemitter potential of transistor 380 is applied also through resistor121R to the base of output transistor 390, appearing in the emittercircuit thereof at point 139 as a positive end weld pulse which is fedby line 61 to the weld timer 12 to cause the latter to terminate theweld interval and extinguish weld current. The end weld signal isdesigned to be a pulse of limited Attention having been directed aboveto the operation of circuitry for determining the termination of theweld time as a function of the weld contact resistance, attention willnow be directed to the operation of supplemental and auxiliary circuitryand, more particularly, the clamp and reset circuit 74 and timers 63,64, 67 (with the memory circuit 71) and 68.

CLAMP AND RESETCIRCUIT 74 At times outside the weld interval, triggertransistors 240 and 250 (FIG. 4) are, respectively, blocking andconductive and clamping transistor 260 normally conducts to drawclamping current through the clamping lines 77, 77a and 77b for holdingthe timers 63, 64, 67 and 68 and the R time base circuit 32 and endratio detector 56 inoperative.

The weld signal (FIG. 71'), here a positive potential, is applied to theinput line 76 of the clamp and reset circuit 74 from beginning to theend of the weld interval by the weld timer 12. Application of suchpositive potential to line 76, in place of the normal low clampingpotential thereon, causes the diode ZIRE to block whereby the later nolonger clamps the anode of diode ZZRE at a low, nonconductive potential.As a result, at the beginning of the weld interval (time 1,, in FIG. 8),diode ZZRE conducts current from the positive potential line 22 throughresistors 61R and 62R to the base of trigger transistor 240 forrendering same conductive.

The trigger circuit 240, 250 is arranged so that it will not switcheasily from one state to another but, when the appropriate conditionsare applied thereto, will switch very rapidly and definitely from onestate to the other. Similar trigger circuits 300, 310 and 310, 330appear on the initial blanking and low limit timers 64 and 67,respectively, and the following detailed description of the operation oftrigger circuit 240, 250 will also serve those succeeding triggercircuits.

With no input'signal applied to its base, transistor 240 is blocked forlack of base drive. Thus, trigger output transistor 240 at its emitterand a fraction of this voltage appears at the emitter of transistor 240due to the voltage divider formed by resistors 64R and 66R. This emittervoltage further biases transistor 240 against conduction.

The trigger circuit 240, 250 has a high degree of noise immunity. Forexample, if resistors 64R and 66R are equal, transistor 240 willnot'conduct easily since it will be necessary for the input signalthereto to morethan equal half the supply voltage existing across lines22 and 23. Moreover, the capacitor 30C aids in filtering out transientsand it will be necessary for transients to have considerable energy tocause transistor 240 to conduct. The type of transients expected toappear in this circuit will not have sufficient energy.

Given a rising input signal to the base of input trigger transistor 240,said transistor will begin to conduct slightly at some point on therise. This slight conduction causes a slight reduction in collectorpotential which in turn results in a slight reduction in current flowthrough output transistor 250 and, hence, in a slight reduction in thebias on the emitter of input transistor 240. This circular actioncontinues rapidly and as a result, the trigger circuit switches, inputtransistor 240 becoming conductive and output transistor 250 blocking.Complete switching occurs typically in less than the microsecond.Collector resistor 65R is preferably substantially larger than emitterresistor 66R so that the emitter voltage of transistor 240 is much lowerwhen it is conducting than when it is blocking. Hence, the input signalto the base of transistor 240 must be greatly reduced from its turn-onvalue before the trigger circuit 240, 250 reset. This feature providesstill more noise immunity.

When the base potential of transistor 240 drops by a sufficient,relatively large amount, the current flow in input transistor 240 willlessen slightly, its collector voltage will rise slightly, outputtransistor 250 will conduct slightly, and as a result, the emitter biason input transistor 240 will rise. This in turn further decreasesconduction of transistor 240. This circular action continues and thus,the transistor 240 rapidly and

